ATTOSWITCH to Present at EuroSOI-ULIS 2026 and ISRDS/ IRDS 2026 Workshops in Granada, Spain

Research outcomes from the ATTOSWITCH project will be presented at the 12^th Joint EuroSOI Workshop and International Conference on Ultimate Integration on Silicon (EuroSOI-ULIS 2026) to be held from May 20 to 22, 2026, in Granada, Spain.

The ATTOSWITCH group at the University of Modena and Reggio Emilia, affiliated to partner IUNET, Italy, will present a paper titled Single Trap and Low Frequency 1/f Noise Modeling in MOSFETs with Dirac Materials or 2D Semiconductor Channel. This work reports a foundational model of noise spectral densities in single layer graphene and MoS₂ MOSFETs considering single traps while establishing it as a basis for 1/f noise.

The ATTOSWITCH group at the University of Udine, also affiliated to partner IUNET, along with their collaborators at CNRS, France, will present a paper titled Ab-initio transport simulations of Dirac Source FETs based on van der Waals Heterojunctions between graphene and functionalized graphene. This work discusses contributions to the interlayer tunnelling and the I_ON in van der Waals DS FETs by using DFT projected orbitals at vdW-HJ. The proceedings of EuroSOI-ULIS 2026 will be published in a forthcoming issue of Solid State Electronics (Elsevier)

ATTOSWITCH will also present the project’s rationale, challenges and perspectives on Dirac Source Field Effect Transistors (DSFETs) at the International Symposium on Roadmapping Devices and Systems (ISRDS), one of the two satellite events of the conference to be held during 18 – 19 May 2026. This event held in conjunction with the International Roadmap for Devices and Systems (IRDS), will unveil latest roadmap updates and future directions in computing, materials and devices, and deliver high‑level insights and discussions shaping the next 15 years of semiconductor innovation. This is the first in-person event of the International Roadmap for Devices and Systems (IRDS) since 2019. It wil be a good opportunity to connect to the roadmapping efforts and position our project in the broader context of long term nanoelectronic technology scaling.